1. Field of the Invention
This invention relates to the field of data processing, and, more particularly, to an improved multiprocessor computing system having an interrupt director on a processor card for directing interrupts from an interrupt controller on a planar board to predetermined ones of plural processors on the card.
2. Description of Related Art
Interrupts are signals generated in response to the occurrence of events external to a processor, which cause the processor to suspend execution of a program, process the interrupt, and then resume execution of the program from the point at which the program was suspended. Hardware interrupts are normally generated by interrupting devices to notify the processor when external events occur. Such events commonly include keystrokes, lapse of periodic time intervals, serial port communications, etc.
Commercially available personal computer systems, such as IBM PS/2 computer systems, include a microprocessor having an interrupt request pin for receiving an interrupt request. An interrupt controller receives interrupts from the interrupting devices, prioritizes the interrupts when more than one interrupt has occurred, and transmits an interrupt request signal to the processor. The interrupt controller also stores an interrupt vector that uniquely identifies the particular interrupt. In response to receiving the interrupt request, the processor then performs an interrupt acknowledge cycle and reads the interrupt vector from the interrupt controller. The processor uses such vector to access and execute an interrupt handler program that processes the particular interrupt.
An example of such a computer system is shown in FIG. 1 which generally illustrates the interrupt system of an IBM model 90 or 95 personal computer 10. Computer 10 includes a processor card 12 plugged into edge connectors 13 on a planar board 11. An Intel 486 microprocessor 14 is mounted on processor card 12 and is connected to a local bus 16 having conventional data, address, control and arbitration lines or busses. Various local devices 18 (such as a level two cache, read only memory devices, or local communication ports), arbitration logic 17, and a dual port memory controller 20 are also connected to bus 16. Memory controller 20 is further connected by a system bus 22 to a direct memory access (DMA) controller 24 and to an expansion bus controller 26.
Memory controller 20 and bus controller 26 are respectively connected to a memory bus 32 and to an expansion bus 28 conforming to the publicly known IBM MicroChannel architecture. (PS/2 and MicroChannel are trademarks of IBM) Busses 32 and 28 extend between processor card 12 and planar board 11 and are respectively connected to system memory 34 and to an interrupt controller 36 and MicroChannel connectors 30. System memory 34 comprises a plurality of dynamic random access memory (DRAM) modules. Connectors 30 provides a plurality of slots for connection to different conventional expansion and I/O devices (not shown). Controller 36 is a cascaded pair of Intel 8259A programmable interrupt controllers (or equivalent) having a plurality of input lines 38 for connection to a plurality of interrupting devices 41. Controller 36 is also connected by a single signal line 40 to interrupt request input pin 42 of microprocessor 14. For simplicity of illustration, the remaining standard pins of microprocessor 14 have been omitted, and pin 42 is omitted from FIG. 2.
When one or more interrupting devices sends an interrupt to controller 36, priority logic 39 determines which interrupt will be first processed and then transmits an interrupt request signal INT on line 40 to the microprocessor. Controller 36 also includes an interrupt vector register (IV REG) 37 for temporarily storing an interrupt vector that identifies the particular interrupt. Computer 10 is configured to handle sixteen different interrupts that are specifically identified by the four low-order bits of the interrupt vector.
Since a number of different events may trigger the single interrupt request signal INT, microprocessor 14 becomes informed of the specific interrupting device by a special protocol known as an interrupt acknowledge cycle or process. In accordance with such process, when controller 36 transmits the INT signal, it also stores an interrupt vector in register 37 from which the vector can be read by the microprocessor. In response to receipt of the INT signal, microprocessor 14 generates an acknowledge cycle during which controller 36 transmits interrupt vector to the processor over the data bus in busses 28, 22 and 16. The interrupt vector is a single byte containing eight bits which uniquely identify which the interrupting device is the source of the interrupt. The specific microprocessor and interrupt acknowledge cycle are described in various publications including "i486.TM. MICROPROCESSOR", published by Intel Corporation, 1989, to which reference may be had for further details.
One of the objectives of the Models 90 and 95 computers was to design the planar board so that the computer can be upgraded by replacing processor card 12 with an upgraded processor card without replacing planar board 11. The upgraded processor card could include a higher performance processor, for example, or it could include plural processors that create a multiprocessor computer. The problem which the present invention addresses is the design of an interrupt handling facility for a multiprocessor system having only one interrupt controller. One possible solution would be to design the system so that all external interrupts are handled by a single processor, but such a design would be disadvantageous because of the possibility of severe software restrictions or performance bottlenecks occurring. Rather than using a single processor to handle and process the interrupts, it is advantageous to design the system so that each interrupting device be capable of interrupting any specific processor.
A possible solution that allows each interrupting device to interrupt any specific processor, would be easy to implement in a personal computer as long as interrupt controller 36 can be modified or duplicated. However, since interrupt controller 36 is on planar board 11 and cannot be modified or duplicated without changing the planar board, it would seem to be impossible to provide a multiprocessor card upgrade, for such models, using an interrupt handling scheme in which each interrupting device is capable of interrupting any specific processor. The invention provides a solution to such problem.
The prior art discloses multiprocessor interrupt handling schemes that differ from that of the invention. U.S. Pat. No. 4,914,570--Peacock discloses a multiprocessor system in which software and processor-to-processor interrupts are used to transfer a process from one processor to another processor.
U.S. Pat. No. 4,933,846--Humphrey et al discloses a large network communications system having a polled interrupt mechanism that supports multiple processors. An interrupt bus is connected to the various processors. Interrupt identifier codes are generated in a timed sequence and transmitted over the interrupt bus to the plural processors. Each processor includes circuitry for recognizing its own identifier code and responding to the interrupt.
U.S. Pat. No. 4,959,781--Rubinstein et al discloses an interrupt handling mechanism for a multiprocessor system. When an interrupt occurs, an attempt is made to assign the interrupt to the currently least-busy processor. The mechanism uses an interrupt bus common to all processors. A dedicated interrupt processor receives signals from external devices and then broadcasts the desired processor and interrupt level across the interrupt bus to all processors.
U.S. Pat. No. 4,965,717--Cutts Jr. et al discloses an interrupt handling mechanism for synchronizing interrupt handling between multiple processors to which interrupts are signalled in parallel. The invention does not require synchronization of interrupts between plural processors.
U.S. Pat. No. 5,067,071--Schanin et al discloses a multiprocessor system having an interrupt handling facility which includes a special vector bus, in addition to normal address, data, and control busses. The requestor or interrupting device determines with the particular CPU or the CPU class for handling the interrupt, and the interrupt vectors are sent to all CPU but are accepted by only the particular CPU selected to handle the interrupt.